Answer: The clock for all digital blocks can be selected from 1 of 16 sources. The possible sources are SysClk, SysClk*2, VC1, VC2, VC3, Comparator buses, Row inputs and other digital blocks. To manage clock skew and ensure that the interfaces between blocks meet timing in all cases, all digital block input clocks must be resynchronized to either SYSCLK or SYSCLK*2, which are the source clocks for all the PSoC device clocking. There are 4 different synchronization options.
1. Sync To SysClk: If the clock to the digital block is derived from SysClk, then the digital block should be synced to SysClk. Even if the clock to the digital block is from an external source through and external pin, it should be synced to Sysclk. Here are some scenarios:
- The digital block uses VC1, VC2 as clock source
- The digital block uses VC3 as clock source and VC3's clock source is VC1, VC2 or SysClk
- The digital block uses another digital blocks output and this other digital block is clocked by any of the above options
- The digital block uses an external clock routed through the Global Input and Row Input nets.
2. Sync to SysClk * 2: If the clock to the digital block is derived from SysClk*2, then it should be synced to SysClk*2. Below are the scenarios
- The digital block uses VC3 as clock and the VC3 clock source is SysClk*2
- The digital block uses another digital block's output as clock and this other digital block has SysClk*2 as its clock source.
3. SysClk Direct: This option is used if the digital block uses SysClk directly as the clock source. If the digital block uses VC1 or VC2 as the clock source and if both VC1 and VC2 dividers are 1, then the synchronization should be set to "SysClk Direct". The Design Rule Checker in the PSoC Designer will generate a warning if the digital block is clocked by VC1 or VC2 and if the combined dividers is 1.
Important Note: If the sync is set to SysClk Direct, this will override the Clock input setting of the digital block and will use SysClk as the clock source.
4. Unsynchronized: This option should be selected only if the digital block is being clocked by SysClk*2. Other than this case, asynchronous operation is not recommended. One other situation where the digital block should be run unsynchronized is when the digital block is clocked by an external clock source and it should be running when the PSoC is in Sleep mode. In Sleep mode, the SysClk is switched off and because of this the block will not work if it is synchronized to SysClk.
Important Note: If the digital block is to operate in sleep mode from an external clock, the Row synchronizer on the Row Input net should also be set to Async. When you click on the small square box at the beginning of the Row Input net, it opens the Digital Interconnect Row_x_Input_x window. In this window, after the Row Input mux, there is a small square box with a clock icon. Click on this and select Async to disable the clock synchronizer on the Row Input.