Answer: Refer the block diagram of ADCINCVR shown below.
An SC Block configured as a modulator converts the input analog signal into a digital bit stream whose On Time density is proportional to the input signal. A PWM gates the output of this modulator into a counter. The counter counts the number of clock cycles the output of the modulator remains ON. At the end of the integration cycle, the value in the counter is the ADC result.
The PWM On time sets the integration period and depends on the resolution of the ADC. For example, if the resolution of the ADC is set to 12 bits, the PWM is on for 4096 data cycles. At the end of the integration cycle, the PWM output goes Low and this stops the counter from counting further till the PWM goes high again for the next cycle.
The CalcTime parameter sets the PWM off time. The PWM should stay off till the CPU reads the counter value, stores the value in the ADC result and restarts the counter. All these operations take place inside the ADC ISR. So, the PWM should stay off till the ADC's ISR is executed. The time depends on the CPU speed as well as the ADC's data clock and is calculated by the formula:
CalcTime >= (180 x Data Clock) / CPU Clock
180 is the number of CPU cycles taken to process the ADC ISR. The CalcTime value should be set to a value equal to or greater than the calculated value.
In case there are other interrupts enabled in the project, interrupt latency introduced by other interrupts should be taken into consideration. The number of clock cycles taken by the longest interrupt should be added to the number 180 in the above formula. For example, if there is an UART present in the design whose interrupt takes 40 CPU cycles to execute, then the number 180 should be replaced by 220 in the above equation.