| Article Index |
|---|
| Basics of PSoC GPIO |
| Drive Modes |
| Registers |
| Writing to a GPIO |
| Reading a GPIO pin |
| Read Modify Write Instructions and Shadow Registers |
| Interrupts |
| GPIO ISR |
| All Pages |
INTRODUCTION
GPIO (General Purpose Input / Output) pins are the bridge between the PSoC and the external world. They are used to connect analog and digital signals to / from the PSoC internals. PSoC has a very flexible GPIO architecture that allows 8 different types of drive modes (not all are available in all families).
GPIO CELL ARCHITECTURE
Following figure shows the block diagram of a GPIO cell. There are two parts in a GPIO cell, the Input path and the Output path.
Input Path: The input path is used to connect an external world signal to the internals of the PSoC. On the digital side, the signal from the pin first passes through a Schmitt trigger. The Schmitt trigger implements the HIGH and LOW input levels corresponding to CMOS logic. The output of the Schmitt trigger connects to the internal data bus, global bus, I2C bus (on selected pins) and to the interrupt logic. The Schmitt Trigger can be disabled in the HighZ Analog drive mode. In this mode, the digital input section is disabled. This mode is generally used for analog input and output to avoid oscillations in the internal digital data bus when the signal level at the input is near the HIGH or LOW thresholds of the Schmitt Trigger.
On the analog side, the pin is directly connected to the internal analog bus.
Output Path: The output path is used to bring out signals from the internals of the PSoC to external world. On the digital side, various signals like Global bus, Data bus and I2C output are multiplexed into the pin Drive logic that has FETs and Pull up / Pull down resistors. The drive logic and the slew control logic control four FETs and two internal Pull Up / Down resistors to select the desired drive mode. More about drive modes in the next section.
On the analog side, the analog output buffers (on P0[2], P0[3],P0[4] and P[5]) are directly connected to the pins. If the drive mode of the pin is set to Strong and if the analog output buffer is enabled, the digital output drive logic will short the analog output buffer to VCC or GND. Relax, there is no need to get alarmed. The PSoC Designer IDE implements strict Design Rule Checks that do not allow such a clash to occur. But when you are manually overriding the drive mode of a pin set by the PSoC Designer IDE, be aware of this issue.
thanks.
BR,
Dustin