Home Programming (Assembly and C) Controlling GPIO using Firmware

Controlling GPIO using Firmware

E-mail Print PDF
( 2 Votes )

Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;}

Question: How do I control a GPIO through the CPU in firmware?

Answer:  To control a GPIO using the CPU, first the GPIO pin should be set to StdCPU mode in the GPIO configuration window in device editor.  The drive mode should be set to any mode other than HighZ or HighZ Analog.  Now the pin may be controlled by writing to the PRTxDR register.  Following are some examples in assembly and C.


Assembly Examples:

or reg[PRT1DR], 0x02     ; Set P1[1]
and reg[PRT1DR], ~0x80   ; Clear P1[7]
xor reg[PRT0DR], 0x04    ; Toggle P0[2]


Notes: Include the m8c.inc file in the assembly source file to refer the PRTxDR registers.  Make sure that the register bank is set to 0, as all the PRTxDR registers are in register bank 0.  The register bank may be set to 0 by using macro M8C_SetBank0


C Examples:

PRT1DR |= 0x02;     // Set P1[1]
PRT1DR &= ~0x80;    // Clear P1[7]
PRT0DR ^= 0x04;     // Toggle P0[2]


Notes: Include the header m8c.h in the C source file to refer the PRTxDR registers.  There is no need to set the register banks in C.  The compiler takes care of the register banks automatically


Care should be taken when a port has both input and output pins and the input pins are configured as Pull Up or Pull down.  Please read article "Read Modify Write Instructions and Shadow Registers"

Tags: PSoC1 GPIO
Comments (2)
  • jf1452  - Shadowing GPIO data registers
    The above methods can cause problems when the GPIO drive mode is set to pull up, or pull down.

    For example:

    If pull up drive mode is selected, the PRTxDR for that bit needs to be set to 1.

    The OR, AND & XOR functions work as follows: Read data from PRTxDR perform bitwise function then write data back to PRTxDR.

    the subtle problem here is that if the pull-up drive pin is being held low; then a 0 will be written back to that pin after the bitwise function has completed.

    The way to overcome this is by using a shadow register for each port; The shadow register is used to hold the desired data and all bitwise functions performed on this data. Once the functions have completed; the shadow register is copied to the output drive register.

    I have attached my functions which I use for your reference. Sorry, the example code is in C only.

    char PRT0DRS; //PRTxDR shadow register
    char PRT1DRS; //PRTxDR shadow register
    char PRT2DRS; //PRTxDR shadow register
    char PRT3DRS; //...
  • graaja
    Hi,
    Thanks for the comments. There is another KB article on this phenomena, namely "Read Modify and Write Instructions and Shadow Registers". I have added a comment in this article to refer to this article as well.
    Best Regards,
    Ganesh
Only registered users can write comments!