Friday, 08 January 2010 15:22
Madhan Kumar K
In a micro controller like PSoC 1 where the maximum Flash size is 32K, code optimization plays a very important role in creating compact code that fits the small flash size of the device. Following are some of the optimization techniques that can be used on PSoC1 projects with the ImageCraft compiler.
Relocatable start code address
This is the address from where the compiler starts placing relocatable code. It has to be set to a value after the end of boot.asm code. The optimal ‘Relocatable start code address’ is right after the end of boot.asm code. When this address is greater than what it needs to be,
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Thursday, 17 December 2009 16:49
Umanath
Question: I have the PSoC operating as an I2C Slave (or Master) with a VDD of 3.3V. It is connected to an external I2C Master (or Slave) operating at 5V. Which voltage should the Pull Up resistors on the SCL and SDA lines be connected?
Answer: Preferably, the pull up resistors should be connected to 3.3V. This will ensure that the PSoC's GPIOs operate at the same voltage as that of VDD.
The pull up resistors can also be connected to the 5V. Under this condition, the internal clamping diodes (refer GPIO cell diagram below) in the GPIO of the PSoC will limit the voltage on the SDA and SCL lines to (3.3V + Diode Voltage). The pull up resistors will also act as current limits which will limit the current through the clamping diodes. Design the Pull up resistors in such a way that the current through the internal clamping diodes is less than 5mA. This is applicable only when the SDA and SCL lines of the other I2C device are also configured as Open Drain mode.
Thursday, 17 December 2009 05:23
M. Ganesh Raaja
When using the UART component in the PSoC, the most important parameter for the UART is the clock. The user module data sheet says the clock to the UART should be 8x the baud clock. So, for a 9600 baud rate, the clock to the UART should be 8 x 9600 = 76.8KHz.
In the PSoC, this clock has to be derived from the SysClk or SysClk * 2. Let us take SysClk for this case and assume a SysClk of 24Mhz. To get a frequency of 76.8KHz from 24MHz, the required divider is 312.5. Unfortunately, we cannot have a fraction in the divider and have to round off to 312 or 313. For a divider of 312, the resulting clock is 76.923KHz. This gives rise to a plethora of questions. Is this clock accurate enough? Will I get bit errors because of the deviation in the clock? What is the maximum tolerance allowed in the clock to UART?
Before we get into the answer to the question, let us first derive the maximum error allowed in the UART clock. Picture below shows the UART RX line and the internal 8x clock. The UART data transfer starts with a Start bit, 8 data bits, optional parity bit and ends with a Stop bit.
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