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This projects shows how to measure multiple Analog inputs using the Analog Mux and Delta Sigma ADC components in PSoC3.  The results are displayed both on an LCD and transmitted to a PC using the UART component.  The results can be observed using Hyperterminal.  The project can be tested using the CY8CKIT-001 PSoC3 Development Kit from Cypress Semiconductors.

Question: How do I set the Baud Rate of the UART component in PSoC3?Answer: There are two ways to set the Baud Rate of the UART component.Option-1: Using the Standard Baud RatesWhen the "Internal Clock" option is enabled in the Advanced tab in the UART component configuration window, the UART configuration window has a drop down list with standard baud rates from 110bps to 921.6kbps.  The baud rate for the UART can be selected from this list.  When this option is used, the PSoC Creator automatically sets the Clock source for the UART component. The below figure shows the screen shot of Baud Rate selection using standard baud rates.

When using the UART component in the PSoC, the most important parameter for the UART is the clock.  The user module data sheet says the clock to the UART should be 8x the baud clock.  So, for a 9600 baud rate, the clock to the UART should be 8 x 9600 = 76.8KHz.In the PSoC, this clock has to be derived from the SysClk or SysClk * 2.  Let us take SysClk for this case and assume a SysClk of 24Mhz.  To get a frequency of 76.8KHz from 24MHz, the required divider is 312.5.  Unfortunately, we cannot have a fraction in the divider and have to round off to 312 or 313. For a divider of 312, the resulting clock is 76.923KHz.  This gives rise to a plethora of questions.  Is this clock accurate enough?  Will I get bit errors because of the deviation in the clock?  What is the maximum tolerance allowed in the clock to UART?Before we get into the answer to the question, let us first derive the maximum error allowed in the UART clock.  Picture below shows the UART RX line and the internal 8x clock.  The UART data transfer starts with a Start bit, 8 data bits, optional parity bit and ends with a Stop bit.

Question: When using UART on CY8C24x94, following DRC warning is generated:“UART should not be used in the CY8C24x94 devices without connection to the USB bus”.Why is this error generated? What should I do if I do not need to connect to the USB bus?Answer: For a UART to work, the error on the clock should be <4%. Both the receiver and transmitter contribute to this error and hence, the clock on the PSoC should not exceed 2% tolerance.  Generally, PSoC devices have an IMO with a tolerance of 2.5%.  But for the CY8C24x94 device, the tolerance is 4%.  So, if the UART clock on the other end of PSoC also has some error, there will be communication errors.  When the USB is used, the IMO is synced with the USB bus clock and becomes very accurate and will prevent any UART errors.  The warning is generated to inform this condition.  There are a few options to follow under this situation.1. Use an accurate External clock with a tolerance of <2% on P1.4 for the SysClk2. If the device at the other end of the UART is driven by a crystal osciallator and does not contribute to the error budget, PSoC can use the 4% error budget and you may not have any problem in the communication. But this is still not a recommended solution.3. Send only 4 bits at a time on the UART.  As the clock tolerance affects only the bits farthest from the start bit, transmitting only 4 bits at a time will prevent bit errors.  The first 4 bits of a UART frame should be the data bits and the next 4 bits should 1's.  So, to send 0x59, you would send 0xF5 first and 0xF9 next. 4. If you are not planning to use the USB, then consider using other family of PSoC devices that have 2.5% tolerance on the IMO.  You could try the CY8C27x43 or the CY8C29x66 families/All things said, the PSoC IMO is trimmed using a trim register in the boot.asm file.  This will increase the accuracy of the clock to atleast <2%.  So, if the PSoC is operating under very normal temperature conditions, you may not get any error at all.  But this approach is definitely risky.

This example project demonstrates using the high level UART User module APIs how to receive and decode a command string with parameters.  A command string with parameters is transmitted from hyperterminal and the project receives and decodes the string and echoes back the command and the parameters.  Use the below link to download the project and documentation from Cypress website.Example Project - UART

Question: How should I select the clock to PSoC 3 UART?  What is the relationship between baud rate and the clock and what are the accuracy requirements?Answer: There are two main points to consider while setting the clock to the UART component.1. When the external clock option is selected for the UART component, the clock should be 8 times the baud rate.  For example:For a baud rate of 19.2kbps, the clock should be 153.6KHz For a baud rate of 115.2kbps, the clock should be 921.6KHzWhen internal Clock option is selected, the PSoC Creator automatically configures the clock input to the UART based on the baud rate selected.2. The tolerance for the UART clock for error free communication is about 4%.  The IMO provides 1% tolerance at 3MHz and 2% tolerance at 6MHz.  So, the clock to the UART may be generated from 3MHz or 6MHz IMO.  The IMO can also be passed through the PLL and can form the clock source for the UART.

Question: I would like to have a digital block running when the PSoC is in Sleep mode.  How do I do this?Answer: When PSoC is in Sleep mode, the IMO is switched Off.  Because of this the SysClk will not be functional.  As all the clock dividers VC1, VC2 and VC3 have SysClk as their source, these clocks cannot be used as the clock source to the digital block that has to be running when the PSoC is in sleep mode.  There are only two clock options.  The first is the internal 32KHz oscillator.  This clock is active even when PSoC is in sleep mode and hence can be used as the clock source to the digital block.  The 32KHz will work even if an External Crystal Oscillator is used.The second option is to use an external clock signal as the clock input to the digital block.  The external clock can be connected to the digital block through the Global Input and Row Input nets.Another important thing to remember is the ClockSync parameter.  As the SysClk is off when the PSoC is in Sleep mode, the ClockSync parameter of the digital block should be set to UnSynchronized.  If the digital block is connected to an external clock source, then the Clock Synchronization on the Row Input net should also be disabled.  Following is the procedure to disable the clock synchronization on the Row Input.Click on the small square box at the beginning of the Row Input net.This opens the Digital Interconnect Row_x_Input_x window.Click on the small square box after the Input Mux and select Async.  This will disable the clock synchronizer on the Row input net.

Question: What is the ClockSync parameter in the PSoC1 digital user modules?  How do I select the value?Answer: The clock for all digital blocks can be selected from 1 of 16 sources.  The possible sources are SysClk, SysClk*2, VC1, VC2, VC3, Comparator buses, Row inputs and other digital blocks.  To manage clock skew and ensure that the interfaces between blocks meet timing in all cases, all digital block input clocks must be resynchronized to either SYSCLK or SYSCLK*2, which are the source clocks for all the PSoC device clocking.  There are 4 different synchronization options.

Question: I have used the UART TX8 user module to implement a serial transmitter along with CSD.  When CSD is started, TX8 stops working.  What is the reason for this and what is the workaround?  Is there a way I can implement a full duplex UART along with CSD?Answer: The CSD user module uses all or few of the VC1, VC2 and VC3 clock dividers depending on the device used (CY8C21x34 or CY8C24x94).  The value of these dividers get configured according to the Scan Speed and Resolution parameters selected in the CSD user module parameters.  When you use the VC1, VC2 and VC3 dividers to generate the clock to the UART, TX8 or RX8 user module, the CSD user module API code overwrites the clock dividers when the CSD_Start function is called.  Following are some of the options that may be used to implement CSD and UART in the same project.

Question:  How do I calculate the clock input to an UART, TX8 or RX8 user module for a given baud rate?  What are the various clock sources that can be used to clock an UART, TX8 or RX8?

Answer: The clock to the UART, TX8 and RX8 modules should be 8 times that of the baud rate.  For example, the clock for a baud rate of 9600 should be 76.8KHz.  As the PSoC is very flexible in terms of clock sources, an UART, TX8 or RX8 can be clocked by VC1, VC2, VC3, SysClk, SysClk*2 as clock source.  Alternately, another digital block may also be used as a clock source.