 Question: When powered On, the PSoC pulls the I2C lines LOW for a brief period. Sometimes, this results in a I2C bus error condition. What is the reason for this glitch and what is the workaround to avoid this glitch? Answer: The I2C SDA and SCL lines are configured as Open Drain Low in the boot.asm after the call to LoadConfigInit function. When the pins are configured as Open Drain Low, the PRT1DR register bits still control the SDA and SCL pins. The default value of the PRTxDR register bits is 0 and this results in the SDA and SCL lines pulled low. In main.c or main.asm when the I2C resource is started, the SDA and SCL lines get connected to the internal I2C hardware and are pulled back to the default HIGH state. The brief time the lines stay low may cause false start conditions or bus error on the I2C bus. There are two workarounds to avoid this behavior. Question: What is the drive mode of the GPIO pins during Power Up? Answer: During Power up, when the internal CPU reset is asserted all the GPIO pins except P1[0] and P1[1] are in High Impedance state. After the CPU reset is released, and the code in boot.asm is executed, the pins get configured to the drive modes as defined in the device configuration. P1[0] and P1[1] are used for ISSP and hence they have a different behavior on Power up. At power up, the internal POR causes P1[0] to initially drive a strong high (1) while P1[1] drives a resistive low (0). After 256 sleep oscillator cycles (approximately 8 ms), the P1[0] signal transitions to a resistive low state. After additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal CPU operation begins. Below is the timing diagram of the P1[0] and P1[1] states during Power On (Extracted from PSoC Technical Reference Manual Section 30.2.1)
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