|
Question: I have the PSoC operating as an I2C Slave (or Master) with a VDD of 3.3V. It is connected to an external I2C Master (or Slave) operating at 5V. Which voltage should the Pull Up resistors on the SCL and SDA lines be connected?Answer: Preferably, the pull up resistors should be connected to 3.3V. This will ensure that the PSoC's GPIOs operate at the same voltage as that of VDD. The pull up resistors can also be connected to the 5V. Under this condition, the internal clamping diodes (refer GPIO cell diagram below) in the GPIO of the PSoC will limit the voltage on the SDA and SCL lines to (3.3V + Diode Voltage). The pull up resistors will also act as current limits which will limit the current through the clamping diodes. Design the Pull up resistors in such a way that the current through the internal clamping diodes is less than 5mA. This is applicable only when the SDA and SCL lines of the other I2C device are also configured as Open Drain mode.
Question: What is the address range that can be used for the EzI2Cs slave user module?Response: When the ROM register parameter is disabled in the EzI2Cs user module, the address range is 0-127. In this mode, the external Master can read or write only to RAM buffers in the I2C Slave. When the ROM register option is enabled, the address range is be 0-63. In this mode, the external Master can read constant values in ROM buffers. The 7th bit of the address is now used to differentiate between the RAM and ROM access. For example, if the address parameter is set to 10 (0x0A), the Master can access the RAM registers using address 0x0A and the ROM registers using address 0x4A.
Question: When I use the I2CHW or EzI2Cs I2C slave interface, the PSoC pulls the SCL line after 8 clocks in a data transfer. Because of this my I2C Master is not able to read or write to the Slave. Why does this happen and what is the solution?Answer: This is called clock stretching and is an expected behavior from an I2C slave. I2C bus can operate from DC to 400KHz and above and the Master is the sole owner of the bus and generates the clock. Devices of various speeds may be mixed in a single I2C bus. In order to allow for slower devices to stay synchronized to the Master (who generates the clock), a feature called clock stretching is implemented in the protocol.
Question: What is the significance of the CPU_Clk_Speed parameter in I2CHW user module? What should be the criteria for selecting the value for the parameter? Answer: The Silicon RevA of the CY27x43 family, with a suffix "A" in the part number (for example CY8C27443A - 24PVXI), had some limitations for the CPU speed while accessing the I2C_CFG, I2C_SCR and I2C_MSCR registers. Details of the restrictions may be found in the Silicon Errata for CY8C27x43 RevA, found here. This project interfaces a PSoC to a 24C256 Serial I2C EEPROM. Project Source: Cypress Semiconductors Question: When powered On, the PSoC pulls the I2C lines LOW for a brief period. Sometimes, this results in a I2C bus error condition. What is the reason for this glitch and what is the workaround to avoid this glitch? Answer: The I2C SDA and SCL lines are configured as Open Drain Low in the boot.asm after the call to LoadConfigInit function. When the pins are configured as Open Drain Low, the PRT1DR register bits still control the SDA and SCL pins. The default value of the PRTxDR register bits is 0 and this results in the SDA and SCL lines pulled low. In main.c or main.asm when the I2C resource is started, the SDA and SCL lines get connected to the internal I2C hardware and are pulled back to the default HIGH state. The brief time the lines stay low may cause false start conditions or bus error on the I2C bus. There are two workarounds to avoid this behavior. |