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Question: What is the difference between the HighZ and HighZ Analog drive modes?Answer: The block diagram of the Input section of a GPIO cell is shown below.The input path has a Schmitt trigger that interfaces the physical GPIO pin to the internal data bus.  In HighZ mode, this Schmitt trigger is enabled, thus connecting the pin to the internal data bus.  So, for using a pin as a digital input, HighZ mode should be used.  If HighZ Analog mode is selected, the internal data bus will always read a logic LOW irrespective of the voltage level on the GPIO pin.In HighZ Analog mode, this Schmitt Trigger is disabled.  This reduces oscillations on the Schmitt Trigger output when the analog input is at the Schmitt Trigger threshold.  So, to use a pin as analog input or output, select HighZ Analog drive mode.

Question: How do I change the drive mode of a PSoC 1 GPIO on the fly?

Answer: The drive mode of the GPIO pin can be changed on the fly by changing the PRTxDMx registers.  There are three drive mode registers for each port that control the drive mode of the pins in a particular port.  These are the PRTxDM0, PRTxDM1 and PRTxDM2 registers. The combination of the bits of these three registers decide the drive mode of a particular pin.  The following table shows the various combinations of the PRTxDMx bits and the corresponding drive modes.

Question: How do I write to a PSoC3 GPIO using firmware?Answer: There are many options to control a PSoC3 GPIO in firmware.  Let us take a look at some of these options and their pros and cons.Option-1: Use Port in APIsWhen a Digital Output Port component is placed in the project, the PSoC Creator generates API functions to control the port pin.  The function used to write to the pin is <Pin Name>_Write.  For example, for a Port Pin component named Out1,

Question:When should I use a Shadow Register to write to a Port? What are Read/Modify/Write Instructions?When I have an input pin configured as pullup, the value of the input gets stuck to 0 irrespective of the state of the input pin.  What could be the problem?Answer: When you have input pins configured as Pull Up or Pull Down and if there are other pins on the same port that are configured as outputs, an instruction that is used to update an output pin may accidentally set or clear the input pin thus latching the input.  For example let us consider the following scenario.

INTRODUCTION

GPIO (General Purpose Input / Output) pins are the bridge between the PSoC and the external world. They are used to connect analog and digital signals to / from the PSoC internals. PSoC has a very flexible GPIO architecture that allows 8 different types of drive modes (not all are available in all families).

Question: When powered On, the PSoC pulls the I2C lines LOW for a brief period.  Sometimes, this results in a I2C bus error condition.  What is the reason for this glitch and what is the workaround to avoid this glitch?

Answer: The I2C SDA and SCL lines are configured as Open Drain Low in the boot.asm after the call to LoadConfigInit function. When the pins are configured as Open Drain Low, the PRT1DR register bits still control the SDA and SCL pins.  The default value of the PRTxDR register bits is 0 and this results in the SDA and SCL lines pulled low.  In main.c or main.asm when the I2C resource is started, the SDA and SCL lines get connected to the internal I2C hardware and are pulled back to the default HIGH state.  The brief time the lines stay low may cause false start conditions or bus error on the I2C bus.  There are two workarounds to avoid this behavior.

Question: What is the drive mode of the GPIO pins during Power Up?

Answer: During Power up, when the internal CPU reset is asserted all the GPIO pins except P1[0] and P1[1] are in High Impedance state.  After the CPU reset is released, and the code in boot.asm is executed, the pins get configured to the drive modes as defined in the device configuration.

P1[0] and P1[1] are used for ISSP and hence they have a different behavior on Power up.  At power up, the internal POR causes P1[0] to initially drive a strong high (1) while P1[1] drives a resistive low (0). After 256 sleep oscillator cycles (approximately 8 ms), the P1[0] signal transitions to a resistive low state. After additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal CPU operation begins. Below is the timing diagram of the P1[0] and P1[1] states during Power On (Extracted from PSoC Technical Reference Manual Section 30.2.1)

 

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Question: How do I control a GPIO through the CPU in firmware?Answer:  To control a GPIO using the CPU, first the GPIO pin should be set to StdCPU mode in the GPIO configuration window in device editor.  The drive mode should be set to any mode other than HighZ or HighZ Analog.  Now the pin may be controlled by writing to the PRTxDR register.  Following are some examples in assembly and C.