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AT25080 from ATMEL is a serial EEPROM with SPI interface.  The device has 8192 bits (1024 bytes) of EEPROM that can be controlled using a 4 wire SPI bus.  This example project demonstrates how to interface a PSoC to this device and read and write an array of data using the SPIM user module.The project and documentation can be downloaded from the below link from Cypress websiteInterfacing the PSoC to an AT25080 Serial EEPROM

Usually PWMs are used for applications like Motor control, LED control etc.  A PWM (Pulse Width Modulator) has a variable pulse width, where the width of the pulse can be varied from 0 to 100% of its period.  In the PSoC, a conventional PWM has a simple down counter and a compare register.  When the value in the Count register is less than or equal to the Compare register the Compare output goes high.  The pulse width of the PWM can be varied by changing the value in the Compare register.  The waveform of a conventional PWM operating at 50% duty cycle and its spectrum plot are shown below.

This example project demonstrates using the high level UART User module APIs how to receive and decode a command string with parameters.  A command string with parameters is transmitted from hyperterminal and the project receives and decodes the string and echoes back the command and the parameters.  Use the below link to download the project and documentation from Cypress website.Example Project - UART

This is a Getting Started Video for PSoC Designer IDE. The video shows how to create a PSoC project to measure an analog signal and display the result on the LCD and also to configure a 16 bit PWM for a 1Hz output to blink an LED. The project is tested using the CY3210 evaluation board from Cypress.  Watch the video below...

Question: How do I change the drive mode of a PSoC 1 GPIO on the fly?

Answer: The drive mode of the GPIO pin can be changed on the fly by changing the PRTxDMx registers.  There are three drive mode registers for each port that control the drive mode of the pins in a particular port.  These are the PRTxDM0, PRTxDM1 and PRTxDM2 registers. The combination of the bits of these three registers decide the drive mode of a particular pin.  The following table shows the various combinations of the PRTxDMx bits and the corresponding drive modes.

Question: How many Clock components can I use in a PSoC 3 design?Answer: PSoC 3 has eight digital clock dividers and four analog clock dividers.  When a Clock component is dragged into the design and "Clock Type" is set to "New", depending on whether the clock is used for a digital or analog peripheral, PSoC creator will use a digital or analog clock divider.  So, if the Clock Type is set to New, we can have eight digital Clock components and four analog Clock components.

Question: How should I select the clock to PSoC 3 UART?  What is the relationship between baud rate and the clock and what are the accuracy requirements?Answer: There are two main points to consider while setting the clock to the UART component.1. When the external clock option is selected for the UART component, the clock should be 8 times the baud rate.  For example:For a baud rate of 19.2kbps, the clock should be 153.6KHz For a baud rate of 115.2kbps, the clock should be 921.6KHzWhen internal Clock option is selected, the PSoC Creator automatically configures the clock input to the UART based on the baud rate selected.2. The tolerance for the UART clock for error free communication is about 4%.  The IMO provides 1% tolerance at 3MHz and 2% tolerance at 6MHz.  So, the clock to the UART may be generated from 3MHz or 6MHz IMO.  The IMO can also be passed through the PLL and can form the clock source for the UART.

Question: I would like to have a digital block running when the PSoC is in Sleep mode.  How do I do this?Answer: When PSoC is in Sleep mode, the IMO is switched Off.  Because of this the SysClk will not be functional.  As all the clock dividers VC1, VC2 and VC3 have SysClk as their source, these clocks cannot be used as the clock source to the digital block that has to be running when the PSoC is in sleep mode.  There are only two clock options.  The first is the internal 32KHz oscillator.  This clock is active even when PSoC is in sleep mode and hence can be used as the clock source to the digital block.  The 32KHz will work even if an External Crystal Oscillator is used.The second option is to use an external clock signal as the clock input to the digital block.  The external clock can be connected to the digital block through the Global Input and Row Input nets.Another important thing to remember is the ClockSync parameter.  As the SysClk is off when the PSoC is in Sleep mode, the ClockSync parameter of the digital block should be set to UnSynchronized.  If the digital block is connected to an external clock source, then the Clock Synchronization on the Row Input net should also be disabled.  Following is the procedure to disable the clock synchronization on the Row Input.Click on the small square box at the beginning of the Row Input net.This opens the Digital Interconnect Row_x_Input_x window.Click on the small square box after the Input Mux and select Async.  This will disable the clock synchronizer on the Row input net.

Question: What is the ClockSync parameter in the PSoC1 digital user modules?  How do I select the value?Answer: The clock for all digital blocks can be selected from 1 of 16 sources.  The possible sources are SysClk, SysClk*2, VC1, VC2, VC3, Comparator buses, Row inputs and other digital blocks.  To manage clock skew and ensure that the interfaces between blocks meet timing in all cases, all digital block input clocks must be resynchronized to either SYSCLK or SYSCLK*2, which are the source clocks for all the PSoC device clocking.  There are 4 different synchronization options.

Question: What is the difference between the Timer and Counter user modules in PSoC 1?

Answer: The Timer is essentially a super-set of the counter.  It can perform all the functions that a Counter can perform, like frequency divider, PWM, generate interrupt on Terminal Count or Compare True etc.

The most important difference between the Timer and Counter is the Capture input of the Timer.  When the Capture input is made HIGH, it acts as enable input like the enable input of a Counter.  When a digital signal is connected to the Capure input, the content of the Timer's count register is latched to the Compare register on the rising edge of the input signal.  By setting the interrupt type to Capture, an interrupt can also be generated on capture event.  This can be used to measure the time difference between two rising edges of the input signal for frequency measurement.

By setting the InvertCapture parameter to "Invert", the capture event will occur on the falling edge of the capture input.  By changing the InvertCapture to Rising and Falling edge (by controlling the "Data Invert" bit in the DxBxxFN register), the timer can be used to measure the pulsewidth of a signal.