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Question: I have an ADC in my application. While debugging, I place a break point after the ADC result is read. Every time the break point is hit, I get different value from the ADC. The input signal to the ADC is very stable. What could be the reason for this behavior? What is the workaround? Answer: ADCs in the PSoC (Incremental or Delta Sigma) are formed by a combination of analog and digital blocks with some processor intervention. An Analog SC block is configured as a modulator and a digital block configured as a counter integrates the modulator's output for a fixed number of data cycles. At the end of the integration time, the value in the counter (which is the ADC result) is read by the CPU. |