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Question: Is it possible to create a Voltage Controlled Oscillator in PSoC3 / PSoC5 using the PSoC3/PSoC5 hardware?Answer: Yes.  With a handful of hardware components, it is possible to create a voltage controlled oscillator in PSoC3 / PSoC5.  The schematic of a voltage controlled oscillator is shown below.

The MPXM2102A series device from Freescale Semiconductors is a silicon piezoresistive pressure sensor providing a highly accurate and linear voltage output — directly proportional to the applied pressure. The sensor is a single, monolithic silicon diaphragm with the strain gauge and a thin–film resistor network integrated on–chip. The chip is laser trimmed for precise span and offset calibration and temperature compensation.  It measures the applied pressure with reference to the built in reference vacuum and provides a differential analog signal.  It measures from 0kPA to 100kPa with a change of 0.2mV/kPa.This example project demonstrates how to use the PSoC1's analogs to measure pressure from this sensor.  An INSAMP and ADCINCVR user modules are used to measure the voltage from the sensor an LCD user module is used to display the measured pressure.  The documentation and project can be downloaded from the below link from Cypress website.Interfacing a MPXM2102A Pressure Sensor

Question: What is the significance of the Analog Power parameter in the Global Resources?  What are the guidelines to select the correct setting?Answer: The Analog Power parameter sets the power at which the internal reference generator operates and also sets the power to the SC blocks of the device.  Below is the excerpt from the Technical Reference Manual from the Analog reference section.The reference array supplies voltage to all blocks and current to the Switched Capacitor blocks. At higher block clock rates, there is increased reference current demand; the reference power should be set equal to the highest power level of the analog blocks used.So, for example, if you have a PGA operating at Medium power and another Comparator operating at High Power, the Reference power should be set to Ref High.  Also, if you have any analog resource that occupies an SC Block (like ADC, DAC, Filters etc), the Reference power should be set to "SC On / Ref xxx".  If the reference is set to "SC Off / Ref xxx", the analog resources placed in the SC Blocks will not work.

Question: What is the CalcTime parameter in an ADCINCVR? How do I set this value?Answer: Refer the block diagram of ADCINCVR shown below.

Question: What is the ClockPhase parameter in the ADC?  How do I set this?Answer: The output of a Switch Capacitor block is not a continuous signal.  SC blocks have two phases of operation.  Phase-1 is the charge acquisition phase when the input signal is sampled.  During this phase, the output of the SC block is 0.  Phase-2 is the charge transfer phase when the acquired charge is transferred to the output and the output is proportional to the ratio of input and output switch capacitor cell values.  So, the output of the SC block is valid only during Phase-2.  Application Note “AN2041 - Understanding Switched Capacitor Blocks” is a very good source of information on this subject.If an ADC’s input is connected to the output of another SC Block,

This is a Getting Started Video for PSoC Designer IDE. The video shows how to create a PSoC project to measure an analog signal and display the result on the LCD and also to configure a 16 bit PWM for a 1Hz output to blink an LED. The project is tested using the CY3210 evaluation board from Cypress.  Watch the video below...

Question:  When I change the input to a Delta Sigma ADC, the result is corrupted.  What is the reason for this?  What are the various factors to be considered while multiplexing the input to a Delta Sigma ADC?Answer: The Delta Sigma ADC is a pipe-lined ADC.  The output is valid only on the second ADC result.  If there is no change in the input signal, all the subsequent results are valid.

Question: What are DNL and INL Errors in an ADC?  Is there anyway to compensate these errors?Answer:DNL - Differential Non-Linearity: For an ideal ADC the output is divided into 2 power n uniform steps each with the width Δ. Any deviation from the ideal step width is the Differential Non-Linearity (DNL). It is expressed as counts. DNL is a function of each ADC's particular architecture.

Question: How do I bring out the VDAC8 output in PSoC 3?  Can I connect the VDAC8 output directly to a pin?Answer: VDAC8 in PSoC3 is implemented by using and IDAC and an internal Load resistance of 16K for 4V range and 4K for 1V range.  Following is the block diagram.

Question: How do I create a High Resolution DAC in PSoC 3?Answer: A High Resolution DAC in PSoC3 may be created by using Dithering.Dithering is a widely used technique in Digital Processing where a noise is intentionally introduced into a system to increase the resolution of the system.  Say we have an 8 bit DAC with a full scale value of 255mV.  Each count of the DAC represents 1mV.  What if we wanted an output of 1.25mV from the DAC.  Switch the DAC output between 1mv and 2mV keeping the output at 2mV 25% of the time and 1mV 75% of the time, the average value of the output would be 1.25mV.  For an output of 1.5mV, the DAC output should be maintained at 2mV for 50% of the time and 1mV 50% of the time.  See diagram below.