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// Start USB for 5V operation and wait till enumeration is completeUSBFS_Start(0, USB_5V_OPERATION);while(!USBFS_bGetConfiguration());// Load the IN endpoint with data with no toggleUSBFS_LoadInEP(1, Data, 8, USB_NO_TOGGLE);while(1)Above code shows the general program flow when using an USBFS user module to send data to the PC using an IN Endpoint.  If you notice, the USBFS_LoadInEP function call before the while loop uses “USB_NO_TOGGLE” and the call inside the while loop uses “USB_TOGGLE”.  What is this TOGGLE and NO_TOGGLE?  What is the significance of these constants?  I can understand from the above code that the first time I call the USBFS_LoadInEP function, I have to use NO_TOGGLE option and TOGGLE for further transactions.  Why is it so?  These are some of the questions a first time user of USB faces.

Many times in applications using the Watchdog timer, there may be a requirement to detect if a reset occurred due to Watchdog or POR / XRES and the application may either start fresh in case of POR / XRES or recover and start executing from the state when the watchdog reset occurred.DETECT THE SOURCE OF RESETThe first requirement is to find out the source of reset.  This can be done by checking the WDRS bit in the CPU_SCR0 register.  This bit is set in case of a watchdog reset event.  The below code in the beginning of main.c can be used.if(CPU_SCR0 & CPU_SCR0_WDRS_MASK)PRESERVE GLOBAL VARIABLESIn order to recover from a watchdog reset and resume the application, it is necessary that the Global variables be preserved when the watchdog reset occurs.  This can be done by setting the IRAMDIS bit in the CPU_SCR1 register.  When this bit is set, all the cells marked “??” in the below table are preserved during a Watchdog reset (taken from Technical Reference Manual Section 3).

In a micro controller like PSoC 1 where the maximum Flash size is 32K, code optimization plays a very important role in creating compact code that fits the small flash size of the device.  Following are some of the optimization techniques that can be used on PSoC1 projects with the ImageCraft compiler.Relocatable start code addressThis is the address from where the compiler starts placing relocatable code.  It has to be set to a value after the end of boot.asm code. The optimal ‘Relocatable start code address’ is right after the end of boot.asm code. When this address is greater than what it needs to be,

Question: I have the PSoC operating as an I2C Slave (or Master) with a VDD of 3.3V.  It is connected to an external I2C Master (or Slave) operating at 5V.  Which voltage should the Pull Up resistors on the SCL and SDA lines be connected?Answer: Preferably, the pull up resistors should be connected to 3.3V.  This will ensure that the PSoC's GPIOs operate at the same voltage as that of VDD. The pull up resistors can also be connected to the 5V.  Under this condition, the internal clamping diodes (refer GPIO cell diagram below) in the GPIO of the PSoC will limit the voltage on the SDA and SCL lines to (3.3V + Diode Voltage).  The pull up resistors will also act as current limits which will limit the current through the clamping diodes.  Design the Pull up resistors in such a way that the current through the internal clamping diodes is less than 5mA.  This is applicable only when the SDA and SCL lines of the other I2C device are also configured as Open Drain mode.

When using the UART component in the PSoC, the most important parameter for the UART is the clock.  The user module data sheet says the clock to the UART should be 8x the baud clock.  So, for a 9600 baud rate, the clock to the UART should be 8 x 9600 = 76.8KHz.In the PSoC, this clock has to be derived from the SysClk or SysClk * 2.  Let us take SysClk for this case and assume a SysClk of 24Mhz.  To get a frequency of 76.8KHz from 24MHz, the required divider is 312.5.  Unfortunately, we cannot have a fraction in the divider and have to round off to 312 or 313. For a divider of 312, the resulting clock is 76.923KHz.  This gives rise to a plethora of questions.  Is this clock accurate enough?  Will I get bit errors because of the deviation in the clock?  What is the maximum tolerance allowed in the clock to UART?Before we get into the answer to the question, let us first derive the maximum error allowed in the UART clock.  Picture below shows the UART RX line and the internal 8x clock.  The UART data transfer starts with a Start bit, 8 data bits, optional parity bit and ends with a Stop bit.

Question: When using UART on CY8C24x94, following DRC warning is generated:“UART should not be used in the CY8C24x94 devices without connection to the USB bus”.Why is this error generated? What should I do if I do not need to connect to the USB bus?Answer: For a UART to work, the error on the clock should be <4%. Both the receiver and transmitter contribute to this error and hence, the clock on the PSoC should not exceed 2% tolerance.  Generally, PSoC devices have an IMO with a tolerance of 2.5%.  But for the CY8C24x94 device, the tolerance is 4%.  So, if the UART clock on the other end of PSoC also has some error, there will be communication errors.  When the USB is used, the IMO is synced with the USB bus clock and becomes very accurate and will prevent any UART errors.  The warning is generated to inform this condition.  There are a few options to follow under this situation.1. Use an accurate External clock with a tolerance of <2% on P1.4 for the SysClk2. If the device at the other end of the UART is driven by a crystal osciallator and does not contribute to the error budget, PSoC can use the 4% error budget and you may not have any problem in the communication. But this is still not a recommended solution.3. Send only 4 bits at a time on the UART.  As the clock tolerance affects only the bits farthest from the start bit, transmitting only 4 bits at a time will prevent bit errors.  The first 4 bits of a UART frame should be the data bits and the next 4 bits should 1's.  So, to send 0x59, you would send 0xF5 first and 0xF9 next. 4. If you are not planning to use the USB, then consider using other family of PSoC devices that have 2.5% tolerance on the IMO.  You could try the CY8C27x43 or the CY8C29x66 families/All things said, the PSoC IMO is trimmed using a trim register in the boot.asm file.  This will increase the accuracy of the clock to atleast <2%.  So, if the PSoC is operating under very normal temperature conditions, you may not get any error at all.  But this approach is definitely risky.

AT25080 from ATMEL is a serial EEPROM with SPI interface.  The device has 8192 bits (1024 bytes) of EEPROM that can be controlled using a 4 wire SPI bus.  This example project demonstrates how to interface a PSoC to this device and read and write an array of data using the SPIM user module.The project and documentation can be downloaded from the below link from Cypress websiteInterfacing the PSoC to an AT25080 Serial EEPROM

The MPXM2102A series device from Freescale Semiconductors is a silicon piezoresistive pressure sensor providing a highly accurate and linear voltage output — directly proportional to the applied pressure. The sensor is a single, monolithic silicon diaphragm with the strain gauge and a thin–film resistor network integrated on–chip. The chip is laser trimmed for precise span and offset calibration and temperature compensation.  It measures the applied pressure with reference to the built in reference vacuum and provides a differential analog signal.  It measures from 0kPA to 100kPa with a change of 0.2mV/kPa.This example project demonstrates how to use the PSoC1's analogs to measure pressure from this sensor.  An INSAMP and ADCINCVR user modules are used to measure the voltage from the sensor an LCD user module is used to display the measured pressure.  The documentation and project can be downloaded from the below link from Cypress website.Interfacing a MPXM2102A Pressure Sensor

Usually PWMs are used for applications like Motor control, LED control etc.  A PWM (Pulse Width Modulator) has a variable pulse width, where the width of the pulse can be varied from 0 to 100% of its period.  In the PSoC, a conventional PWM has a simple down counter and a compare register.  When the value in the Count register is less than or equal to the Compare register the Compare output goes high.  The pulse width of the PWM can be varied by changing the value in the Compare register.  The waveform of a conventional PWM operating at 50% duty cycle and its spectrum plot are shown below.

This example project demonstrates using the high level UART User module APIs how to receive and decode a command string with parameters.  A command string with parameters is transmitted from hyperterminal and the project receives and decodes the string and echoes back the command and the parameters.  Use the below link to download the project and documentation from Cypress website.Example Project - UART