Answer: When PSoC is in Sleep mode, the IMO is switched Off. Because of this the SysClk will not be functional. As all the clock dividers VC1, VC2 and VC3 have SysClk as their source, these clocks cannot be used as the clock source to the digital block that has to be running when the PSoC is in sleep mode. There are only two clock options.
The first is the internal 32KHz oscillator. This clock is active even when PSoC is in sleep mode and hence can be used as the clock source to the digital block. The 32KHz will work even if an External Crystal Oscillator is used.
The second option is to use an external clock signal as the clock input to the digital block. The external clock can be connected to the digital block through the Global Input and Row Input nets.
Another important thing to remember is the ClockSync parameter. As the SysClk is off when the PSoC is in Sleep mode, the ClockSync parameter of the digital block should be set to UnSynchronized. If the digital block is connected to an external clock source, then the Clock Synchronization on the Row Input net should also be disabled. Following is the procedure to disable the clock synchronization on the Row Input.
- Click on the small square box at the beginning of the Row Input net.
- This opens the Digital Interconnect Row_x_Input_x window.
- Click on the small square box after the Input Mux and select Async. This will disable the clock synchronizer on the Row input net.