Answer: This is called clock stretching and is an expected behavior from an I2C slave. I2C bus can operate from DC to 400KHz and above and the Master is the sole owner of the bus and generates the clock. Devices of various speeds may be mixed in a single I2C bus. In order to allow for slower devices to stay synchronized to the Master (who generates the clock), a feature called clock stretching is implemented in the protocol.
The I2C lines are configured as Open Drain pins with external pull up resistors. This implements a wired AND configuration. Each slave can pull the clock low till it can process the previous bit of data. The slave releases the SCL line when it has processed the data. Only when all the slaves in the bus have released the SCL line, the Master can generate the next clock. The PSoC I2C hardware is fully compliant to the I2C specification. The I2C hardware generates an interrupt on various events like when an address byte has been received from a Master, when a Data byte has been received from the Master or when the Master has read a data from the slave. Upon this interrupt, the hardware pulls low the SCL line and the CPU enters the I2C ISR to process the interrupt. Inside this ISR, the CPU performs tasks like address comparison, transferring received data to the buffer, preparing the next data for the Master etc. After completing the operations, the SCL line is released and the Master can now read the ACK Bit.
The solution to this problem is to make the Master compliant with the I2C protocol. The Master after writing a high to the SCL line should poll the SCL line and wait till the SCL line becomes high. This indicates that all the slaves in the bus have released the SCL line. The Master should generate the next clock only after this happens.