Question: What is the drive mode of the GPIO pins during Power Up?
Answer: During Power up, when the internal CPU reset is asserted all the GPIO pins except P1[0] and P1[1] are in High Impedance state. After the CPU reset is released, and the code in boot.asm is executed, the pins get configured to the drive modes as defined in the device configuration.
P1[0] and P1[1] are used for ISSP and hence they have a different behavior on Power up. At power up, the internal POR causes P1[0] to initially drive a strong high (1) while P1[1] drives a resistive low (0). After 256 sleep oscillator cycles (approximately 8 ms), the P1[0] signal transitions to a resistive low state. After additional 256 sleep oscillator clocks, both pins transition to a high impedance state and normal CPU operation begins. Below is the timing diagram of the P1[0] and P1[1] states during Power On (Extracted from PSoC Technical Reference Manual Section 30.2.1)
